1. Field of the Invention
The present invention relates to a semiconductor wafer and a manufacturing method thereof.
2. Description of the Background Art
In a conventional SOI (Silicon On Insulator or Semiconductor On Insulator) wafer, an oxide film layer resides on one main surface of a supporting substrate wafer made of, e.g. a silicon substrate, and an SOI layer resides on the top surface of the oxide film layer. Such SOI and oxide film layers are formed by bonding to the supporting substrate wafer an SOI layer wafer that has a silicon substrate with an oxide film formed on its main surface and then removing part of it.
After the supporting substrate wafer and the SOI layer wafer are bonded together, an unwanted portion of the SOI layer wafer is removed by adopting a method such as SMART CUT(Registered Trademark) or ELTRAN(Registered Trademark); refer to Patent Document 1 shown below.
When a MOS (Metal Oxide Semiconductor) transistor is formed in the SOI layer, it is arranged so that its channel direction is parallel to a <100> crystal direction of the SOI layer, for example. It is known that arranging the channel direction in parallel with <100> crystal direction enhances the current driving capability of the P-channel MOS transistor by about 15 percent and also reduces the short-channel effect.
It is thought that the current driving capability is enhanced because the hole mobility in <100> crystal direction is larger than that in <110> crystal direction, and that the short-channel effect is reduced because the value of the boron diffusion coefficient in <100> crystal direction is smaller than that in <110> crystal direction.
Now, with SOI wafers, the SOI layer wafer, in which SOI and oxide film layers are formed, may be bonded to the supporting substrate wafer with their crystal directions shifted at 45° (or 135°) with respect to each other. Specifically, the two wafers are bonded together in such a way that a <100> crystal direction of the SOI layer and a <110> crystal direction of the supporting substrate wafer coincide with each other. The reason is shown below.
(100) wafers cleave along {110} crystal planes. Accordingly, when the SOI layer wafer and the supporting substrate wafer are bonded together so that the <100> crystal direction of the former coincides with the <110> crystal direction of the latter, the wafer can be cleaved, for experiments and studies, along {110} cleavage planes of the supporting substrate wafer 1 that forms a large part of the wafer thickness. On the other hand, in the SOI layer whose crystal direction is shifted, an MOS transistor can be formed so that its channel direction is parallel with a <100> crystal direction.
Thus, when cleaved, the supporting substrate wafer 1 breaks along <110> crystal direction, while the SOI layer breaks along <100> crystal direction. In this way, bonding the two wafers with their crystal directions shifted from each other provides the advantage that a section along the MOS transistor channel direction can be easily exposed.
The following list shows prior art reference information related to the present invention:
Patent Document 1: Japanese Patent Application Laid-Open No. 2002-134374,
Patent Document 2: Japanese Patent Application Laid-Open No. 9-153603 (1997), and
Non-Patent Publication 1: G. Scott et al., “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress,” (US), IEDM, 1999.
A conventional SOI wafer is manufactured by a method shown below, for example.
First, an SOI layer wafer and a supporting substrate wafer are prepared, both of which are a (100) wafer having a (100) plane as a main surface. Next, a notch (or an orientation flat) is formed at a <100> crystal direction edge of the SOI layer wafer and a notch (or an orientation flat) is formed at a <110> crystal direction edge of the supporting substrate wafer. Then, the two substrates are bonded together in such a way that the <100> crystal direction of the SOI layer and the <110> crystal direction of the supporting substrate wafer coincide with each other.
In this bonding process, the two wafers are bonded so that the notch of the supporting substrate wafer and the notch of the SOI layer wafer coincide with each other. However, when the two wafers are positioned by utilizing these notches only, the SOI layer <100> crystal direction and the supporting substrate wafer <110> crystal direction may not be precisely aligned.
With such a positioning error between wafers, the MOS transistor channel direction cannot be precisely aligned with the SOI layer <100> crystal direction and a deviation is caused between the two. This is because MOS transistors are formed on the basis of the position of the supporting substrate wafer.
Then the current driving capability of the MOS transistors cannot be enhanced satisfactorily. Furthermore, electric characteristic variations will occur among MOS transistors formed on the surfaces of different SOI wafers.